1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly data read and write circuits of a dynamic random access memory (which will also be referred to as a “DRAM” hereinafter).
2. Description of the Background Art
A hierarchical data I/O (input/output) line structure and a direct sensing system have been used as techniques for satisfying demands for large capacities and high operation speeds of semiconductor memories in recent years.
With increase in capacity of memories, parasitic capacitances of I/O lines may increase and cause remarkable delay in signal transmission. The hierarchical I/O line structure is employed for reducing an influence of this delay by hierarchically arranged I/O lines. For example, the hierarchical I/O line structure is described, e.g., in “Ultra LSI Memory” (Kiyoo ITO, BAIFUKAN), pp. 167–170.
The direct sensing system is a technique having such a feature that the operation speed is increased by directly taking memory cell signals onto I/O lines without waiting for amplification by sense amplifiers, and is disclosed, e.g., in “Ultra LSI Memory” (Kiyoo ITO, BAIFUKAN), pp. 165–167.
FIG. 31 schematically shows an I/O line structure of a semiconductor memory device 500 having a typical hierarchical I/O line structure.
Referring to FIG. 31, a memory cell array of a semiconductor memory device 500 is divided into a plurality of sense amplifier blocks 501 of k in number. A sense amplifier S/A amplifies data read onto bit line pair BL and /BL provided correspondingly to a column of memory cells. Sense amplifiers S/A in each sense amplifier block are activated independently of those in other sense amplifier blocks.
The I/O lines provided for transmitting output data are divided into lines I/O1–I/O3 which are hierarchically arranged for reducing an influence of delay in data transmission caused by increase in parasitic capacitance. Further, main amplifiers MA1 and MA2 are arranged for amplifying potential differences occurring on I/O lines I/O2 and I/O3, respectively.
According to the above structure, a column decoder/driver 502 controls a column select signal, and thereby the sense amplifier amplifies the data on the bit line pair of the corresponding column and transmits the same onto the data I/O line. In general, it is I/O1 in which increase in parasitic capacitance may cause a problem. Therefore, I/O1 is divided, and data lines I/O2 crossing I/O1 are connected to divided I/O1 with switches therebetween, respectively.
Further, upper or high-order data lines I/O3 connected to the plurality of lines I/O2 are arranged. Thereby, the device can perform fast input/output of a large quantity of data as a whole. In particular, lines I/O2 can have a simple structure, and therefore can be arranged on the memory cell array so that lines I/O2 do not significantly increase a chip area.
According to the above system, however, many switches controlling connection between the I/O lines are required, resulting in disadvantageous increase in chip area.
FIG. 32 conceptually shows a semiconductor memory device employing a typical direct sensing system, and particularly a structure of a column select circuit 510 relating to read and write of data.
Referring to FIG. 32, word line WL and a bit line pair BL and /BL are arranged correspondingly to a memory cell MC. Column select circuit 510 includes sense amplifier S/A for amplifying data on the bit line pair, a read select circuit 511 for reading data from the memory cell, a write select circuit 512 for writing data into the memory cell, a read data line pair RO and /RO and a write data line pair WI and /WI.
When word line WL is activated, the data in memory cell is read onto bit line pair BL and /BL, and is amplified by sense amplifier S/A activated by sense amplifier activating signals φN and /φP A read gate transistor 513 or 514 included in read select circuit 511 is turned on by the data read onto bit line pair BL and /BL, and directly drives data read line pair RO and /RO in accordance with selection by a read column select signal YR. Thereby, a voltage difference occurring on read data line pair RO and /RO is amplified and taken out. In this manner, the data stored in the memory cell can be read out.
Data writing is performed by writing the data, which is transmitted onto write data line pair WI and /WI, onto bit line pair BL and /BL in accordance with selection by a write column select signal YW.
As described above, the direct sensing system increases the speed of data read operation by directly driving the read data line pair based on the memory cell signal read onto the bit line pair.
Although the speed of data read operation can be increased, disadvantageous increase in number of circuit elements and increase in layout area occur because the column selection in the read operation is performed independently of that in the write operation, and additional read gate transistors are required.
For improving production yields while increasing capacities of memories, such a structure is employed that a memory cell array includes a preliminary memory cell array having a spare line (a spare row or a spare column) for each unit of rows or columns, and a failed memory cell having a defect is repaired by replacing the row or column containing the failed memory cell with the spare line. Thus, a so-called redundant repair structure is employed.
FIG. 33 conceptually shows a structure of a redundant repair circuit 520 in the redundant repair structure.
Referring to FIG. 33, redundant repair circuit 520 includes a spare memory cell array 521 in which spare rows or columns are arranged, and program elements 525a and 525b which are arranged correspondingly to the spare row and spare columns, respectively.
Each of program element 525a and 525b is formed of a program fuse which can be blown by laser applied thereto, or a thin insulating film to be broken by a high voltage for turning on the element.
For example, when a defect occurs in a memory cell at (x1, y1), i.e., a row address x1 and a column address y1 in a regular memory cell array, processing is externally effected on the program element for replacing the whole regular row at row address x1 with one spare row. Naturally, processing may be performed to use the spare column based on column address y1.
When the address of row or column containing the defective memory cell is determined, the redundant repair structure can repair a defect in the regular memory cell by replacement with the spare row or column of the spare memory cells based on the state of program elements in the above manner. Thereby, the redundant repair structure can reduce a product rejection rate of semiconductor memory devices.
In the conventional redundant repair structure, however, the program elements are provided for both the rows and columns of the preliminary memory cell lines. Therefore, the chip having a huge capacity requires a significantly large chip area due to increase in number of the program elements.
Since transistors forming the memory cells have been scaled down in accordance with increase in capacity, increase in number of the transistors does not cause a significant problem in the area of the preliminary memory cell array. However, the program elements such as fuse elements are less scaled down compared with the memory cells. Accordingly, increase in number of the program elements significantly increases the layout area.